Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level
Paper Title : Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level Thermal effects are rapidly gaining importance in nanometer CMOS technologies. Increased power density, coupled with spatio-temporal variability of chip workloads, causes on-die temperature non-uniformities. The assumption of a uniform temperature for the delay and power analysis of a large CMOS circuit produces inaccurate results. For this reason, significant design margins are taken to ensure safe operation. To improve design quality, we need precise localization of hotspots at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis needs to be done at…
A System Level Approach to Multi-core Thermal Sensors Calibration
I am the second author of this paper. Paper presented at PATMOS11, Spain. The paper is mainly about calibration of thermal sensors in the Intel Single-chip Cloud Computer. The paper is available via springer.
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer
I am the Second author of this paper! This paper is presented at, DATE12 conference, in Dresden, Germany. In this paper we use the Intel Single-Chip cloud computer as a test platform and we quantify the effect of frequency scaling of CPU cores on the execution speed and energy consumption of different parallel multi-core benchmarks. Download : DATE12_paper Abstract : Dynamic frequency and voltage scaling (DVFS) techniques have been widely used for meeting energy constraints. Single-chip many-core systems bring new challenges owing to the large number of operating points and the shift to message passing interface (MPI) from shared memory communication.…
Single-Chip Cloud Computer Thermal Model
Paper presented at THERMINIC11 conference, Paris, 2011. This paper presents a thermal model for Intel Single-chip Cloud Computer. The thermal model is mainly based on Hotspot. Download : Sadri_THERMINIC11 Abstract : Spatial and temporal non-uniformities of workload and power consumption advanced Systems-on-Chip (SoC) platforms result in localized high power densities, which lead to temperature hot-spots, gradients and thermal cycles that may cause non-uniform ageing and accelerated chip failure. The Single-Chip Cloud Computer (SCC) is an experimental many-core processor created by Intel Labs and it integrates thermal sensors to track the chip thermal behavior. Unfortunately these sensors provide a limited introspection on…
MiMAPT: Adaptive Multi-Scale Thermal Analysis at RT and Gate Level
The first paper related to MiMAPT software is presented at THERMINIC12 workshop, Budapest, 2012. This paper introduces MiMAPT, a tool that I developed to do thermal, power and timing analysis of integrated circuits while accounting for on-die temperature non-uniformity. Download Paper : sadri_therminic12 Brief : Tight timing/area constraints produce on-chip layouts with non-regular shapes for RTL entities. Thus, grid-like floorplans where RTL entities are abstracted as rectangular blocks for thermal simulation lead to inaccurate results. In addition, spatial and temporal variability of chip workload causes localized temperature variations. Exact localization of hotspots at gate-level necessitates an extremely detailed spatial resolution which is…
Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh
Paper to be presented at DATE14 Conference, Dresden, Germany, 27 of March, 2014. This paper mainly talks about development of a TLM platform to simulate the operation, power and temperature distribution in 3D MPSoCs built using Wide-I/O DRAMs. Download Paper : sadri_DATE14 Abstract : Heterogeneous 3D integrated systems with Wide-I/O DRAMs are a promising solution to squeeze more functionality and storage bits into an ever decreasing volume. Unfortunately, with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. We improve DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting…
Energy and Performance Exploration of Accelerator Coherency Port Using Xilinx ZYNQ
A paper presented at FPGAWorld13 Conference, Stockholm, 2013. The paper mainly talks about the energy and speed of performing hardware acceleration in the Xilinx ZYNQ device using the Accelerator Coherency Port (ACP). With this paper, I provide complete source code for the entire hardware and software developed for the Xilinx ZYNQ device to perform all of the evaluations. In order to obtain the software please write me through your official email account. Download Paper : sadri_fpgaworld13 Abstract: Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed and energy. Efficient management of data sharing…