Lesson 8 – An Overview on ZYNQ Architecture
This session is a brief overview of the architecture of Xilinx ZYNQ device. It tries to talk about why this architecture can be useful for many computational tasks. It shows the internals of the ZYNQ Programmable System (PS) briefly. It discusses the AXI interfaces between the PS and the PL in the ZYNQ device. Furthermore, it looks at the most important documents available for the ZYNQ device. The ZYNQ PL is also discussed briefly. For this session there exist four videos. Three are created at the studio of Electrical engineering department and the other is my screen cast. each of…
Estimating Power at RTL using Synopsys Design Compiler
Estimation of power consumption of an integrated circuit at RT level can be handy since it allows designers to obtain an approximate and yet accurate enough estimate on total power consumption of their design in a very short time. Basically, the designer runs the logic simulation for his pure RTL design and obtains the switching activity statistics for his circuit. The test bench developed by the designer for the logic simulation is indeed the workload imposed to the circuit and power will be estimated for this specific workload. In this writing I go through the details of how power estimation…
Lesson 7 – AXI Stream Interface In Detail (RTL Flow)
In this lesson we continue our exploration of AXI Stream Interfaces. We choose a pure RTL design approach during this lesson. We use the Vivado's "Create and Package IP" capability to create a simple unit which contains one AXI stream master interface and another custom general purpose interface. We go through the RTL source code of the design, and we change the RTL produced by vivado to add our own customizations. In another example, we create a design containing two AXI stream input interfaces and one AXI stream output interface this time using Vivado and in Verilog. At the final…
How to use the Xilinx VDMA core on the ZYNQ device
THIS POST GETS COMPLETED GRADUALLY ! I DON'T HAVE ALL OF THE INFORMATION RIGHT NOW ! In this post, I go through the procedure of adding a Video DMA to your ZYNQ PL in Vivado environment and then to program it. Camera : First you need the camera to be connected to your ZED Board. For this, there is a very nice reference design that you can use: ZEDBOARD OV7670 The source design is also provided so you can make sure that your camera is working and the data is being received by the PL correctly. If you don't have…
Ideas for doing Bachelor/Master thesis project with the ZYNQ device – 1
I was thinking of ideas for students to do their bachelor or master degree thesis with the Xilinx ZYNQ device. Development of A Windows CE BSP for the ZYNQ: Currently, there is a company, Adeneo which is providing a board support package (BSP) for the ZYNQ. This is however not coming free. In my idea it would be very useful to assess the possibility of creating a BSP for the ZYNQ device using what Microsoft and Xilinx provide as free material. Later this BSP can be provided to all other people for free and even enhanced versions can be sold…
Lesson 6 – AXI Stream Interfaces In Detail (HLS)
In this lesson we focus on AXI stream interfaces. We use the Vivado HLS and create a set of example designs. The first one is a simple counter which sends the count values over its AXI stream master interface. The next example is the counter but with an additional AXI stream slave interface through which one can configure the counting range of the counter. Finally we create a module which contains one General Purpose I/O (GPIO) input and one AXI stream master output. The module receives the data over GPIO and sends them through the streaming interface. For each of…
Lesson 5 – Designing with AXI using Xilinx Vivado – Part II
In this video I bring more practical examples of how you can create an AXI based sub-architecture including some AXI slaves, AXI masters and AXI Interconnect. I Introduce the Xilinx AXI Central DMA Controller component and I used it in the example. I focus on the key points of defining suitable address maps for the components residing on an AXI interconnect. I also try to give a preview of some of the potential problems. Then I show how you can convert your Block Design inside Vivado into a Packaged IP and how you can instantiate it in another project. Presentation…
Synopsys VCS : libvcsnew.so: undefined reference to …
I have seen this very strange problem with Synopsys VCS time to time. It is actually not related to if you are using the 32 Bits or 64 Bits version and on which type of system you are running the tool. For both of the pure 32 bits and pure 64 bits runs I have seen this problem occurs. Synopsys indicates that this problem might happen when you have several installations of the VCS on your system however, I have seen this problem on systems that I am pretty sure have just once instance of VCS. Ineed I don't know…
Gate Level Simulation and Initializing Registers to Prevent X Propagation
Today I was trying to Simulate an Optimized version of OpenRISC CPU at Gate level. To Synthesize the core I had used one of the ASIC technology nodes that we have in the laboratory and I wanted to obtain estimates on power consumption of OpenRISC under different workloads. Obviously, the best way to obtain the power consumption is to obtain circuit switching activity at Gate Level or RTL (refer to MiMAPT paper) and then to feed them to the tool for power estimation. In order to do that I had to perform a Post-synthesis or Post-route simulation on the OpenRISC…
Lesson 4 : Designing with AXI using Xilinx Vivado
In this lesson we demonstrate a practical example in which we use the Xilinx Vivado environment and we create a sample AXI based architecture. This lesson shows the primary skills of designing with AXI under Vivado environment. As our main AXI master, we use the Microblaze CPU core. Then we add several different AXI slave components to the system. The purpose is to show how these AXI based components get connected to each other inside the Vivado environment. The purpose is not to build a fully functional system. This lesson contains a presentation, a Vivado TCL script (Gzipped tar format)…