ZYNQ Ultrascale+ and PetaLinux (part 15): rootfs on SD card with X and Qt libraries
We configure PetaLinux to have its root file system on the second partition of the SD card. We then go through the steps required for preparing the SD card, creating disk partitions, formatting them and copying required PetaLinux files to each of the partitions.
ZYNQ Ultrascale+ and PetaLinux (part 14): Build with X and Qt Libraries enabled
We use Xilinx BSP provided for ZCU104 to build PetaLinux with the X (graphical user) environment enabled. We also customize PetaLinux root file system to include Qt Libraries. We then build the SDK that we need later for building Qt applications.
ZYNQ Ultrascale+ and PetaLinux (part 13): Graphical User Interface and Qt Applications (i)
In this video we start looking at bringing up PetaLinux with its graphical user interface (X server) enabled. We talk briefly about the GPU block available inside Zynq ultrascale+ EG and EV devices. We briefly describe our flow for compiling petalinux. We show the primary view of our user application in Qt.
ZYNQ Ultrascale+ and PetaLinux (part 12): FPGA Pin Assignment (LVDS Data Capture Example)
In this video we go through a simplified example design which transfers data between two chips at a total rate of ~ 5 GBits/s using LVDS signals. We look at how pin locations can affect the final timing of the design.
ZYNQ Ultrascale+ and PetaLinux (part 11): FPGA Pin Assignment (PCIe example)
We continue with our simple PCI Express design example in this video and we show two different pin assignment scenarios for this design. We show how pin assignment can affect the quality of the place and route in the design.
ZYNQ Ultrascale+ and PetaLinux (part 10): FPGA Pin Assignment (with brief look at LVDS and PCIe)
First section of the video on Pin assignment. We look at pin assignment done for our ZCU104 based vivado project. We try to cover other topics briefly as well, we look at MIPI CSI2 RX IP as an example case, we also do pin assignment for a X4 Gen3 PCIe interface. We briefly talk about each of the High Density and High Performance IO Banks. This video is to be continued on the next part.
Dynamic Function Exchange with ZYNQ Ultrascale+ : Part 7: Standalone Application C Code
We go through the C source code of the standalone application that we have written for our partial reconfiguration example. Our standalone application configures and runs the DMA engines, also it performs the required partial reconfiguration task which allows dynamic exchange of the function of each of our 3 reconfiguration partitions.
Dynamic Function Exchange with ZYNQ Ultrascale+ : Part 6: Standalone Software Config
In this video we continue within Vitis environment. We create our standalone software project using the XSA file from Vivado design. We add the required libraries for partial reconfiguration to the BSP. We also update the linker script.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 5: Vivado Outputs and starting Vitis
Part 5 of Dynamic Function Exchange (DFX) (Partial Reconfiguration) with ZYNQ Ultrascale. In this part we look at the outputs of vivado project. we look at created partial bistreams, we discuss how these bitstreams can be used for changing the functionality of our reconfigurable blocks dynamically. We export the XSA file and run the vitis environment.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 4: Partial Reconfiguration Flow (2)
In this video we go through the steps done in vivado to enable partial reconfiguration, assign modules to partial reconfigurable partitions, and define run-time configurations.