Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level
Paper Title : Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level
Thermal effects are rapidly gaining importance in nanometer CMOS technologies. Increased power density, coupled with spatio-temporal variability of chip workloads, causes on-die temperature non-uniformities. The assumption of a uniform temperature for the delay and power analysis of a large CMOS circuit produces inaccurate results. For this reason, significant design margins are taken to ensure safe operation. To improve design quality, we need precise localization of hotspots at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis needs to be done at multiple levels of granularity using a versatile thermal floorplan. We propose MiMAPT, an approach for analyzing delay, power and temperature in digital circuits. MiMAPT integrates seamlessly into major industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Thermal analysis is done at register-transfer (RT) and then gate-level considering non-regular shapes of on-die units with multiple scales of resolution and speed. To demonstrate the capability of MiMAPT in temperature variation aware delay/power estimation, a widely used IP block is chosen and four different chips are implemented using 65 nm and 40 nm (LVT, HVT) technology nodes. Different temperature patterns are then applied to the design. Accuracy improvements of up to 28% for static power and 16% for minimum clock period are reported in comparison with uniform averaged temperature assumption. Evaluating the ability of MiMAPT in multi-scale thermal analysis, a speed-up of 98× is reported compared to fine-grained method, while keeping false negatives at zero and the error of temperature estimation below 0.05 °C.
Download Link for the paper: Here.
سلام به استاد گرامی
به خاطر نیکی بزرگی که در حق جوانان این مملکت کردید از خدا می خواهم که عاقبت به خیر بشوید و در هر دو جهان خیر ببینید
سلام استاد گرامی
ممنون می شوم اگر راهنمایی بفرمائید برای microblaze-virtex5 جهت اندازه گیری performance، دما، power و … با توجه به فاکتورهای branch predictor، cache miss و … از چه simulator هایی می شود استفاده کرد؟
متشکرم
Salam Ostad,
Would you please let me to know what simulators are useful to measure performance, power, thermal and etc with respect to cache miss, branch predictor factors in microblaze-Virtex5?
Thanks in advance
Hi. As I said before, I personally do not think that MicroBlaze is a suitable target CPU for this type of research.
If that was me, for modelling the CPU core and processing subsystem, I would use GEM5 and ARM v7 CPU cores.
Look at my paper at DATE14 (listed in my papers list), there we have built a system with ARM cpu cores which runs android to measure the power consumption of the system and eventually to estimate temperature.
However if you want to stick to Microblaze I suspect there is no such functional model for it like the GEM5. In this case, the best way to go is to put it on the real hardware measure the power consumption on the real FPGA. There you need to find the signal which gets enabled when a cache miss happens and you have to keep track of its statistics.