Many students write me regarding possible ideas to do projects using FPGAs. 

Here based on my experience in recent years and based on what I see more important, I list a set of ideas which can be considered as suitable and useful targets for doing projects on the Embedded FPGA design topic.

First things first! Connectivity!

Suppose that you have implemented a computational unit on the FPGA. The first question which raises is how do you connect this guy to the rest of the system so that you can use it efficiently?

In fact, most of the times we have a system on the FPGA. The system contains various blocks and each block is responsible for a specific task. For example, our system contains, a microprocessor core, a UART interface, a SD card reader, a FFT calculation unit, and so on…

The question is how do you connect all of these guys together efficiently? The answer is system-on-chip buses! Examples of this buses include : WishBone, PLB, and AXI.

Among these three the AXI is the most useful. So my first suggestion is that the student should obtain a basic understanding of the AXI bus.

Then later when you use either Xilinx or Altera development environments to create your system on the FPGA, you will see that all of the blocks get connected to each other using AXI.

So whatever module, we are going to implement as a project, we better make sure that it comes with an AXI interface so that later other people can easily plug it to the rest of their system.

Possible Projects

Here is a small list of possible targets for the projects on Embedded FPGA design, which can be also used by other people and can be very handy.

  1. An AXI Floating Point Unit : We take the FPU of OpenCores we arm it with an AXI interface.
  2. Different types of Cryptography engines with AXI interfaces. (e.g. elliptic curve cryptography)
  3. A CPU core with Morphing capability. By morphing we mean the CPU core is capable of changing its architecture according to the type of work-load that it is executing. (to get more idea look at this paper)
  4. Updating the UltraSparc T1 to talk AXI. In this project we take the Simply RISC core and make it enable of talking AXI directly. The result will be very useful for many people around the globe.
  5. The 32 Bits AXI PicoBlaze ! The idea here is to have the stable and versatile PicoBlaze CPU core, then to increase its data-bus width to 32 Bits and then to add AXI plugs to its ports. This in my idea will be again another really useful design.
  6. The AXI OpenRISC. The basic idea is to have the OpenRISC core (either 1K or 1.2K or 2K) talking directly AXI. This is some thing I have already done. But my OpenRISC core doesn’t have the data and instruction caches. The idea can be to have a fully functional OpenRISC core talking directly AXI.

Might you be interested in doing any of the above projects (of course considering the required background knowledge which you should have already gained through your FPGA design courses), you can write me and I will help you through them as much as I can.

TLM Modelling 

One excellent way of simulating the operation of a hardware or doing exploration in the design & architecture space of a system containing various computational blocks, is to use Transaction Level Modeling.

TLM modeling is not necessarily a tool for doing hardware verification only, but it can be a tool for modeling the operation of hardware at different levels of accuracy. Indeed, we can develop several transaction level models at several levels of accuracy for one piece of hardware and each time, based on the level of accuracy that we need, we use the suitable TLM model, balancing the speed of simulation and its accuracy.

In my idea, projects related to development of TLM models (specially Approximately Timed Models) for of the aforementioned CPU cores is very useful and valuable.