Dynamic Function Exchange with ZYNQ Ultracale+ : Part 5: Vivado Outputs and starting Vitis
Part 5 of Dynamic Function Exchange (DFX) (Partial Reconfiguration) with ZYNQ Ultrascale. In this part we look at the outputs of vivado project. we look at created partial bistreams, we discuss how these bitstreams can be used for changing the functionality of our reconfigurable blocks dynamically. We export the XSA file and run the vitis environment.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 4: Partial Reconfiguration Flow (2)
In this video we go through the steps done in vivado to enable partial reconfiguration, assign modules to partial reconfigurable partitions, and define run-time configurations.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 3: Partial Reconfiguration Flow (1)
In this video we briefly review the vivado project that we have prepared for our partial reconfiguration flow. We address key points that need to be considered for partial reconfiguration. Design source codes and deliveries are available upon a fair donation.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 2: Vivado Project
This is the second hobby video for partial reconfiguration series. In this video we start looking at the Vivado design that we use to show the partial reconfiguration flow. We create the design step by step and describe every part.
Dynamic Function Exchange with ZYNQ Ultracale+ : Part 1: Introduction
Introduction to new series of hobby videos on Dynamic Function Exchange (Partial Reconfiguration) for ZYNQ Ultrascale+ devices. Contents apply to other Xilinx FPGAs as well.
ZYNQ Ultrascale+ and PetaLinux (part 9): nVidia Jetson AGX Xavier SPI & Xilinx ILA (Section 2)
NOTE: At nVidia Jetson side, the screen capture frame rate was very low. So in the video you will see the parts I am showing Jetson screen at a lower frame rate. Part 9 Video
ZYNQ Ultrascale+ and PetaLinux (part 8): nVidia Jetson AGX Xavier SPI & Xilinx ILA (Section 1)
Part 8 has 2 sections, each section in one video. We look at setting up the SPI Interface of nVidia Jetson AGX Xavier. We describe the hardware setup and the experiment we want to perform. We briefly look at System ILA IP at our ZCU104 vivado project Part 8 Video
ZYNQ Ultrascale+ and PetaLinux (part 7): Folder structure, Vivado Projects (SPI, IIC,…)
Welcome to part 7 of ZYNQ Ultrascale+ and PetaLinux videos. In this video we briefly describe the folder structure of deliverable package for these video series. We go through the Vivado projects for both of the ZCU104 and ZED boards. We describe the design architecture. We talk about the custom AXI Slave SPI cores. We produce the bitstream and XSA files for both of the board projects. These will be used for the coming videos. Video Part 7
ZYNQ Ultrascale+ and PetaLinux (part 6): recap, updates next steps
Part 6 of the series about running PetaLinux on ZYNQ Ultrascale+. The updated hardware architecture is shown in this video. It contains the following 3 boards: 1) NVIDIA Jetson AGX Xavier 2) Xilinx ZCU104 3) Digilent ZED board I briefly discuss the architecture that we want to implement and our goals. These series will continue. Jetson, Xavier are trademarks of NVIDIA. ZYNQ, ultrascale are trademarks of Xilinx. Video Part 6
ZYNQ Ultrascale+ and PetaLinux – part 5 – SPI, I2C and GPIO interfaces (Building PetaLinux)
In this video I go through the steps required for building petalinux for ZCU102 board. Design sources are available upon a donation to Part 5 Video