Lesson 7 – AXI Stream Interface In Detail (RTL Flow)
In this lesson we continue our exploration of AXI Stream Interfaces. We choose a pure RTL design approach during this lesson.
We use the Vivado’s “Create and Package IP” capability to create a simple unit which contains one AXI stream master interface and another custom general purpose interface. We go through the RTL source code of the design, and we change the RTL produced by vivado to add our own customizations.
In another example, we create a design containing two AXI stream input interfaces and one AXI stream output interface this time using Vivado and in Verilog.
At the final stage of this lesson, we create another example AXI based peripheral which contains one memory mapped AXI slave interface and one AXI stream master interface. The target is to allow the written data to the AXI memory mapped interface to flow over the AXI stream interface.
Presentation : axi_stream_rtl_part_I
Watch online : Video Part I
Watch online : Video Part II
Watch online : Video Part III
Watch online: Video Part IV
Watch online: Video Part V
Watch online: Video Part VI
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When do you expect this tutorial to be released?
Hello, just wanted to say thanks for those videos. I’m learning much from watching them. It gives a good grasp of the various paradigms available in Vivado to conceive stuff for Zynq. So much abstraction, meh.
Xilinx’s official documentation hasn’t been quite as useful to the beginner that i am, you’re doing remarkable work there.
Hi, you are welcome. I should emphasize on the point that you should always consult the Xilinx documentation for your projects. That is the main reference. What I show you in these videos are just aimed to accelerate your learning. good luck.
Hello,
Thanks a lot for your great videos i just want to tell you that i have been searching for months for something to make me understand the AXI protocol and vivado tool without any result, you are GREAT
Hello, thank you so much for your brilliant work. It is really helpful for our work. Looking forward for your other update, especially on the internal RTL detail in custom IP interface. Thanks again.
Hello, your training videos are very helpful and we really appreciate your contributions. BTW, can you show more instruction about how exchange stream data through the AXI_ACP port?
Hi, Yes! soon I will go to AXI Memory Mapped interfaces and designing modules with AXI MM interfaces and there I talk extensively about the ACP port.
dear
thank you alot
i start read xilinx documentation at the beginning but i was very confused
after i watch your video :: i get the right road
but please can you design your module in vhdl!!
if you can not. can you guide me to specific web page
Hi. VHDL and Verilog provide you both with the same level of capability in design. But, I don’t like VHDL :P, so I keep preparing the example designs in verilog. Meanwhile, the xilinx sample code generated by vivado, is available most of the times in both verilog and vhdl. So you can select your favorite language.
As-salamu alaykum Mohammad,
I really appreciate your tutorial videos, it’s very useful for me and I learn a lot from them. I hope so you continue uploaded new videos with different topic where the most important topics for me is Timing analysis and constrains files. it’s difficult to understand the concept of timing and I need some help from you.
By the way, I have question regarding to AXI stream signals. When I add AXI Slave or Master to my new created IP, the Vivado dose not add all signals like: TDEST, TID, and TUSER. I tried to add them from IP Package, but I could not. So, what I should to do now; shell I add these signals manually as you have add EN, AXI_EN, and FRAME_SIZE ? If yes how can I do that. Or there are another away to add those missing signals.
Best Regards,
Eng. Tariq Alsharif
Hi. If you have created an AXI Stream interface using the custom peripheral generation wizard of Vivado , and the AXI Stream port does not contain TUSER and TLAST signals (I am in doubt!) then just add them manually.
Hello Mohammad,
I am following along with the videos, during the logic simulation of the sample generator, I had to modify the test bench to get the ‘Clk’ signal do something (100MHz clock)
the line ‘forever #5 Clk = -Clk’ needed to be changed to ‘forever #5 Clk = !Clk’
not sure why this is, but thought it could be useful to other viewers.
thanks a lot for the great videos !
Ronny
Hi
that is ~ sign on the top left corner of your keyboard.
Might you have mistakenly types – (subtract) ? 😉
Hello, First I would like to thank you for the great Tutorial videos, they are really helpful.
Could we get the tcl scripts of the sessions?
Hello
Dear Mr.sadri
very thanks for your perfect videos.
i am beginner in ZYNQ . so i start learning with your videos. i have two question :
1)is necessary to have zed board or any evaluation board for my learning?
2)do you suggest any benefit document?
very thanks for your corporation
i think it is better to have a zynq board in hand while learning. zybo or zed board or micro zed are all fine.
Hello Mr.Sadri ,
Thanks for your video training .
I have a question:
I have data coming serially from adc(audio codec) .If i am right , it is 1 bit every clock cycle how can i store these data and create 16bits width of data from each bit coming serially ? is there an IP block which does it ? or should i write a RTL code ?
Thanks in advance
David.
hi. i think we discussed this through emails. all you need to do is to create a custom module with an axi stream master port and an input for the serial stream of data.
Hi
very thanks for your videos training. 🙂
I have a question:
Why did you use ” AXI4_stream_data FIFO”? why didn’t you choose ” FIFO_Generator” ip?
thanks alot .
the fifo generator is also completely fine. you can use it. there is no specific reason why i chose the axi stream fifo.
hello Sir,
Your design is exactly the same as i want for my project. But i stuck in SDK programming. So, can you help me in building software application.
thank you,
Princy
Hello Mr Sadri,
Very thanks for your videos training. all are very useful. well done.!
I went through this lesson. but i am not able to create customise ip of (sample generator). how did you create counter and customise with axi stream interface?
Could you please send me mail of these three verilog file of axi stream interface?
Thanks lot,
Regards
Anand
I just want to congratulate you for this work.
Thank you Mr. Sadri.
Hello, thanks for your videos, I am your follower, I watch the video that you did for microelectronics Systems also, it is very useful, I am working in a project for the university, I downloaded the sources files from Microelectronics Systems site for the image rotary project, but I didn’t find the file mycores(pixel_buffer_blk_mem, ill_axi_controller cores) want to know if you can help me with information about how to create this cores.
Thank you for your tutorials.
you can produce those cores with vivado. first one is a block memory. second one is an ila.
Hi Dr. Sadri,
Thanks so much for these hobby/training videos. I really like the level of detail, pace, and knowledge you bring.
So far I worked through Session 07, Part VI of RTL Flow. Unfortunately the website does not have links to part VII and on. Do those videos exist? Can you post them to your website?
Thanks again.
I just viewed Lesson 8 and now understand that Lesson 7’s topic is continued in later videos. So, you may disregard my original question about “missing” videos.
Thanks again.
Hi,
I referred your video for understanding and learning the data transfer between DDR3 SDRAM and PL of Zynq and implementing it same for ZC702 board.. I implemented the example you demonstrated in your “Zynq Training- Session 7- Part III”..
I am facing an error when I run “Validate” in Vivado after generating block diagram..
[BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axi_dma_0/S_AXIS_S2MM(SampleGenTest_processing_system7_0_0_FCLK_CLK0) and /xfft_0/M_AXIS_DATA(SampleGenTest_processing_system7_0_0_FCLK_CLK1)
I have routed and configured all the IP block the same way as explained in the video session.. I am not able to figure what can be the problem..
Please suggest or advise me how i can resolve this.. I have uploaded the error screen shots (https://drive.google.com/open?id=1luEXmO0-StbYiMg9yRBfkkg1apcfH6no) and my project directory on this link (https://drive.google.com/open?id=1L1NLh_Jsi7dxuWiH5HD97OUMki_LYgxA)
Many Thanks in Advance,
Dhara
Dear Sir,
First of all I would like to thank you for the great job you have done doing the ZYNQ training videos. They have been very useful for me.
I am working with a zedboard, and I am trying to replicate the project you have done in lesson 7 (fft ip).
Is there any chance to get the code so I don´t have to write it, because I have tried it but gives me some errors.
Thank you
King regards
sources are available upon a fair donation andres.
I have done small donation for your help. Please add my email id in your dropbox so that i can access other videos and code.
Thanks for your sharing !!
Platform: Xilinx Zynq
Email:
Hello Mr. Sadri,
Thank for your elaborate lectures on AXI, DMA and Zynq. Its really helping me reduce my learning curve. Thanks again. Keep up your good work.
Thanks
Ashik
Hi , I have donated for your video lectures, How can I access the source code?
wrote you an email
my “t_valid” and data are not going low when “En” becomes low(=0)i forget the hdl code for this part it was in which part the valid and then data showed be low when En is low
I think if you write a testbench and run some simulations you can easily find out where is the issue.