Lesson 6 – AXI Stream Interfaces In Detail (HLS)
In this lesson we focus on AXI stream interfaces.
We use the Vivado HLS and create a set of example designs. The first one is a simple counter which sends the count values over its AXI stream master interface. The next example is the counter but with an additional AXI stream slave interface through which one can configure the counting range of the counter. Finally we create a module which contains one General Purpose I/O (GPIO) input and one AXI stream master output. The module receives the data over GPIO and sends them through the streaming interface.
For each of the designs, we develop a test bench and we verify the functionality of the design by going through the waveforms obtained from simulations.
We then go through synthesis and implementation of this block. We then import the output packaged IP created by Vivado HLS into vivado and we instantiate it in a sample design. We should how these modules can be connected to the rest of design through examples.
Presentation: axi_stream_in_detail
Course Video: Watch Online
Course Design Files: source_codes
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Hi Mohammad;
Thank you for your lessons. They are very useful.
I have tried to follow the lesson 6 but when I insert the your cpp code, I have a problem.
In the directive pannel appears:
axi_interface_counter and inside counterValue, but counter_output does not appear.
I’m using Vivavo HLS 2014.1.
Thank you.
Hi,
I tried using the latest vivado hls, and every thing looks fine! In the directives panel, I can see counter_output and counterValue.
It is strnage why counter_output is not shown in your case.
Hi.
It’s really strange. I could send you a screenshot to your email.
I too had this problem. Watch https://www.youtube.com/watch?feature=player_detailpage&v=r6fhj5Kp-7k#t=551
He sets the Top Function. If you don’t specify the Top Function, you don’t get the input and output directives, just the static variables.
I also had the same problem. Solution: cpp file and Top Function names should be same. In tutorial it is axi_interface_counter.
From where could i download the source codes for some of this ? . Kindly let me know
Alsalam Alaykom
Kindly when I can find source file for the current training course.
BR
Hi Karim, you need to kindly make a donation to have access to design sources.
Salam Dr. Mohammad Sadri,
I have a question. I have generated an IP core using vivado HLS. the top function is following.
typedef std::complex< ap_fixed > data_t
#define N 3
int TopSimple(data_t in1[N],data_t in2[N], data_t out[N])
{
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE s_axilite port=in1
#pragma HLS INTERFACE s_axilite port=in2
#pragma HLS INTERFACE s_axilite port=out
int index;
for(index=0;index<N;index++)
{
out[index]=in1[index]+in2[index];
}
return 0;
}
can you help me that how i can input array in1,in2 to generated IP in xsdk?
Thanks alot.
Waiting for your help.
Regards
Abbas
I don’t understand neither your question neither the code. Are all of the ports axi stream slaves??
Hi,
Where I can find DVE program to simulate my IP core’s? I am searching it few hours without effect. Is it possible to run DVE on Windows?
Thanks in advance !
dve, if i recall correctly, this is the synopsys waveform viewer tool.
Selamun aleykum i’m student from turkey and I have a problem. This problem is about this lessen (HLS). My problem is when I synthesis my project step by step, syn folder not included in my solution. I’m using vivado 2018.1 what cant I do please help me
Hello Cemal, I will try to have a look if i make time. meanwhile if you found the solution, it would be awesome if you also post it here.