Lesson 7 – AXI Stream Interface In Detail (RTL Flow)
In this lesson we continue our exploration of AXI Stream Interfaces. We choose a pure RTL design approach during this lesson. We use the Vivado's "Create and Package IP" capability to create a simple unit which contains one AXI stream master interface and another custom general purpose interface. We go through the RTL source code of the design, and we change the RTL produced by vivado to add our own customizations. In another example, we create a design containing two AXI stream input interfaces and one AXI stream output interface this time using Vivado and in Verilog. At the final…
How to use the Xilinx VDMA core on the ZYNQ device
THIS POST GETS COMPLETED GRADUALLY ! I DON'T HAVE ALL OF THE INFORMATION RIGHT NOW ! In this post, I go through the procedure of adding a Video DMA to your ZYNQ PL in Vivado environment and then to program it. Camera : First you need the camera to be connected to your ZED Board. For this, there is a very nice reference design that you can use: ZEDBOARD OV7670 The source design is also provided so you can make sure that your camera is working and the data is being received by the PL correctly. If you don't have…
Ideas for doing Bachelor/Master thesis project with the ZYNQ device – 1
I was thinking of ideas for students to do their bachelor or master degree thesis with the Xilinx ZYNQ device. Development of A Windows CE BSP for the ZYNQ: Currently, there is a company, Adeneo which is providing a board support package (BSP) for the ZYNQ. This is however not coming free. In my idea it would be very useful to assess the possibility of creating a BSP for the ZYNQ device using what Microsoft and Xilinx provide as free material. Later this BSP can be provided to all other people for free and even enhanced versions can be sold…
Lesson 6 – AXI Stream Interfaces In Detail (HLS)
In this lesson we focus on AXI stream interfaces. We use the Vivado HLS and create a set of example designs. The first one is a simple counter which sends the count values over its AXI stream master interface. The next example is the counter but with an additional AXI stream slave interface through which one can configure the counting range of the counter. Finally we create a module which contains one General Purpose I/O (GPIO) input and one AXI stream master output. The module receives the data over GPIO and sends them through the streaming interface. For each of…