Lesson 5 – Designing with AXI using Xilinx Vivado – Part II
In this video I bring more practical examples of how you can create an AXI based sub-architecture including some AXI slaves, AXI masters and AXI Interconnect. I Introduce the Xilinx AXI Central DMA Controller component and I used it in the example. I focus on the key points of defining suitable address maps for the components residing on an AXI interconnect. I also try to give a preview of some of the potential problems. Then I show how you can convert your Block Design inside Vivado into a Packaged IP and how you can instantiate it in another project. Presentation…
Synopsys VCS : libvcsnew.so: undefined reference to …
I have seen this very strange problem with Synopsys VCS time to time. It is actually not related to if you are using the 32 Bits or 64 Bits version and on which type of system you are running the tool. For both of the pure 32 bits and pure 64 bits runs I have seen this problem occurs. Synopsys indicates that this problem might happen when you have several installations of the VCS on your system however, I have seen this problem on systems that I am pretty sure have just once instance of VCS. Ineed I don't know…
Gate Level Simulation and Initializing Registers to Prevent X Propagation
Today I was trying to Simulate an Optimized version of OpenRISC CPU at Gate level. To Synthesize the core I had used one of the ASIC technology nodes that we have in the laboratory and I wanted to obtain estimates on power consumption of OpenRISC under different workloads. Obviously, the best way to obtain the power consumption is to obtain circuit switching activity at Gate Level or RTL (refer to MiMAPT paper) and then to feed them to the tool for power estimation. In order to do that I had to perform a Post-synthesis or Post-route simulation on the OpenRISC…
Lesson 4 : Designing with AXI using Xilinx Vivado
In this lesson we demonstrate a practical example in which we use the Xilinx Vivado environment and we create a sample AXI based architecture. This lesson shows the primary skills of designing with AXI under Vivado environment. As our main AXI master, we use the Microblaze CPU core. Then we add several different AXI slave components to the system. The purpose is to show how these AXI based components get connected to each other inside the Vivado environment. The purpose is not to build a fully functional system. This lesson contains a presentation, a Vivado TCL script (Gzipped tar format)…
Lesson 3 : AXI Stream Interface
This lesson talks about the other kind of AXI interfaces : AXI stream So far we were showing only AXI memory mapped interfaces however for most of the data-flow applications AXI Stream interface is the main mechanism to connect processing units together. This lesson shows the principles of AXI stream interfaces, and talks about connecting AXI stream and AXI memory mapped devices together. Presentation Download : Videos In English: What is AXI Interface? (Watch Online) Please make a donation if the videos have been useful for you.