Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh
Paper to be presented at DATE14 Conference, Dresden, Germany, 27 of March, 2014. This paper mainly talks about development of a TLM platform to simulate the operation, power and temperature distribution in 3D MPSoCs built using Wide-I/O DRAMs. Download Paper : sadri_DATE14 Abstract : Heterogeneous 3D integrated systems with Wide-I/O DRAMs are a promising solution to squeeze more functionality and storage bits into an ever decreasing volume. Unfortunately, with 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated. We improve DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting…
Energy and Performance Exploration of Accelerator Coherency Port Using Xilinx ZYNQ
A paper presented at FPGAWorld13 Conference, Stockholm, 2013. The paper mainly talks about the energy and speed of performing hardware acceleration in the Xilinx ZYNQ device using the Accelerator Coherency Port (ACP). With this paper, I provide complete source code for the entire hardware and software developed for the Xilinx ZYNQ device to perform all of the evaluations. In order to obtain the software please write me through your official email account. Download Paper : sadri_fpgaworld13 Abstract: Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed and energy. Efficient management of data sharing…